Senior ASIC Engineer - DSP - ASIC design - RTL - 802.11 - VLSI jobs in Minneapolis, MN - - - - Send This Job to a Friend Search More Jobs CyberCoders - Be Selective Location Minneapolis, MN; Bloomington, MN
SemiconductorTALENT.com, a division of Intelligent Technology Solutions, is a North American leader in providing executive search services to the microelectronics and engineering sectors We are seeking a SR Digital ASIC Designer - with DSP Expertise, wireless/802.11, for our St-Paul, MN based client RESPONSIBILITIES: - Full lifecycle design of wireless DSP ASICs. - DSP algorithm Verilog/VHDL implementation tradeoff analysis - Spec, architect, RTL coding, behavioural modeling, synthesis/simulation, verification
Job Title Lead Engineer-ASIC Job ID Number 519487 Company Advanced Information Systems Location Bloomington, MN Job Category Information Technology Job Description Job Description: Responsible for definition, design, verification and documentation for ASIC development. Determines architecture design, logic design and system simulation. Defines module interfaces/formats for simulation. Evaluates all aspects of the process flow from high level design to synthesis, place and route, and timing and power utilization
Hitachi Global Storage Technologies, Inc.|Rochester, MN, 55901|
Job Description ASIC top level and block level verification using Modelsim and System Verilog Verification testbench creation and model development Work in a cohesive team environment with other verification and design engineers to debug and resolve complex issues involving ASIC design and verification Communicate well with firmware engineers, management, and customers to determine requirements, document schedules, convey status, and resolve issues Documentation/application note development Foster
We are seeking a SR Digital ASIC Designer - with DSP Expertise, wireless/802.11, for our Minneapolis, MN based client RESPONSIBILITIES: - Full lifecycle design of wireless DSP ASICs. - Design complex wireless DSP ASIC's. - DSP algorithm Verilog/VHDL implementation tradeoff analysis - Spec, architect, RTL coding, behavioural modeling, synthesis/simulation, verification, etc.. Job Requirements: QUALIFICATIONS: - BS or better in EE - 8+ yrs experience in DSP algorithm Verilog/VHDL implementation tradeoff
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